B2.64 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1

The ID_AA64PFR1_EL1 provides additional information about implemented core features in AArch64.

Bit field descriptions

ID_AA64PFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-50 ID_AA64PFR1_EL1 bit assignments
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RES0, [63:8]
RES0

Reserved.

SSBS, [7:4]
AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe (SSBS).
0x01
AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe, but does not implement the MSR/MRS instructions to directly read and write the PSTATE.SSBS field.
RES0, [3:0]
RES0

Reserved.

Configurations

There are no configuration notes.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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