B1.80 SCR, Secure Configuration Register

The SCR defines the configuration of the current Security state when EL3 is implemented and can use AArch32.

It specifies:

  • The Security state, either Secure or Non-secure.
  • What mode the core branches to if an IRQ, FIQ, or External Abort occurs.
  • Whether the CPSR.F or CPSR.A bits can be modified when SCR.NS==1.

Bit field descriptions

SCR is a 32-bit register.

Figure B1-69 SCR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


This register resets to value 0x00000000.

Configurations

This register is only accessible in Secure state.

AArch32 System register SCR can be mapped to AArch64 System register SCR_EL3, but this is not architecturally mandated.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.