B1.80 SCR, Secure Configuration Register

The SCR defines the configuration of the current Security state when EL3 is implemented and can use AArch32.

It specifies:

  • The Security state, either Secure or Non-secure.
  • What mode the core branches to if an IRQ, FIQ, or External Abort occurs.
  • Whether the CPSR.F or CPSR.A bits can be modified when SCR.NS==1.

Bit field descriptions

SCR is a 32-bit register.

Figure B1-69 SCR bit assignments
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This register resets to value 0x00000000.


This register is only accessible in Secure state.

AArch32 System register SCR can be mapped to AArch64 System register SCR_EL3, but this is not architecturally mandated.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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