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The SCR defines the configuration of the current Security state when EL3 is implemented and can use AArch32.
SCR is a 32-bit register.
This register resets to value
This register is only accessible in Secure state.
AArch32 System register SCR can be mapped to AArch64 System register SCR_EL3, but this is not architecturally mandated.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.