B1.4 AArch32 registers by functional group

This section identifies the AArch32 registers by their functional groups and applies to the registers in the core that are implementation defined or have micro-architectural bit fields.

Reset values are provided for these registers.

Identification registers

Name Type Reset Description
AIDR RO 0x00000000

B1.9 AIDR, Auxiliary ID Register

CCSIDR RO

-

B1.15 CCSIDR, Cache Size ID Register

CLIDR RO

UNK

Unknown: [31:30], [25:24], [22:21], 8, 5

'b1: [1:0]

'b0: [29:26], 23, [20:9], [7:6], [4:2]

B1.16 CLIDR, Cache Level ID Register

If the L2 cache is not implemented, the value is:

0x09200003

CSSELR RW

0x00000000, [2:0] UNK.

B1.26 CSSELR, Cache Size Selection Register

CTR RO

0x84448004

B1.27 CTR, Cache Type Register

ID_AFR0 RO

0x00000000

B1.59 ID_AFR0, Auxiliary Feature Register 0

ID_DFR0 RO 0x03010066

B1.60 ID_DFR0, Debug Feature Register 0

Bits [19:16] are 0x1 if ETM is implemented, and 0x0 otherwise.

ID_ISAR0 RO

0x02101110

B1.61 ID_ISAR0, Instruction Set Attribute Register 0

ID_ISAR1 RO

0x13112111

B1.62 ID_ISAR1, Instruction Set Attribute Register 1

ID_ISAR2 RO

0x21232042

B1.63 ID_ISAR2, Instruction Set Attribute Register 2

ID_ISAR3 RO

0x01112131

B1.64 ID_ISAR3, Instruction Set Attribute Register 3

ID_ISAR4 RO

0x00011142

B1.65 ID_ISAR4, Instruction Set Attribute Register 4

ID_ISAR5 RO

0x00011121

B1.66 ID_ISAR5, Instruction Set Attribute Register 5

ID_ISAR5 has the value 0x00010001 if the Cryptographic Extension is not implemented and enabled.

ID_ISAR6 RO

0x00000010

B1.67 ID_ISAR6, Instruction Set Attribute Register 6

ID_MMFR0 RO

0x10201105

B1.68 ID_MMFR0, Memory Model Feature Register 0

ID_MMFR1 RO

0x40000000

B1.69 ID_MMFR1, Memory Model Feature Register 1

ID_MMFR2 RO

0x01260000

B1.70 ID_MMFR2, Memory Model Feature Register 2

ID_MMFR3 RO

0x02102211

B1.71 ID_MMFR3, Memory Model Feature Register 3

ID_MMFR4 RO

0x00021110

B1.72 ID_MMFR4, Memory Model Feature Register 4

ID_PFR0 RO

0x00000131

B1.73 ID_PFR0, Processor Feature Register 0

ID_PFR1 RO

0x10011011

B1.74 ID_PFR1, Processor Feature Register 1

Bits [31:28] are 0x1 if the GIC CPU interface is implemented and enabled, and 0x0 otherwise.

MIDR RO 0x412FD050

B1.76 MIDR, Main ID Register

MPIDR RO -

B1.77 MPIDR, Multiprocessor Affinity Register

REVIDR RO

0x00000000

B1.79 REVIDR, Revision ID Register

VMPIDR RW -

B1.89 VMPIDR, Virtualization Multiprocessor ID Register

The reset value is the value of MPIDR.

VPIDR RW 0x412FD050

B1.90 VPIDR, Virtualization Processor ID Register

Implementation defined registers

The following table shows the 32-bit wide implementation defined Cluster registers. These registers are RW, and details can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual

Table B1-5 Cluster registers

Name Copro CRn Opc1 CRm Opc2 Width Description
CLUSTERCFR cp15 c15 0 c3 0 32-bit Cluster configuration register.
CLUSTERIDR cp15 c15 0 c3 1 32-bit Cluster main revision ID.
CLUSTEREVIDR cp15 c15 0 c3 2 32-bit Cluster ECO ID.
CLUSTERACTLR cp15 c15 0 c3 3 32-bit Cluster auxiliary control register.
CLUSTERECTLR cp15 c15 0 c3 4 32-bit Cluster extended control register.
CLUSTERPWRCTLR cp15 c15 0 c3 5 32-bit Cluster power control register.
CLUSTERPWRDN cp15 c15 0 c3 6 32-bit Cluster power down register.
CLUSTERPWRSTAT cp15 c15 0 c3 7 32-bit Cluster power status register.
CLUSTERTHREADSID cp15 c15 0 c4 0 32-bit Cluster thread scheme ID register.
CLUSTERACPSID cp15 c15 0 c4 1 32-bit Cluster ACP scheme ID register.
CLUSTERSTASHSID cp15 c15 0 c4 2 32-bit Cluster stash scheme ID register.
CLUSTERPARTCR cp15 c15 0 c4 3 32-bit Cluster partition control register.
CLUSTERBUSQOS cp15 c15 0 c4 4 32-bit Cluster bus QoS control register.
CLUSTERL3HIT cp15 c15 0 c4 5 32-bit Cluster L3 hit counter register.
CLUSTERL3MISS cp15 c15 0 c4 6 32-bit Cluster L3 miss counter register.
CLUSTERTHREADSIDOVR cp15 c15 0 c4 7 32-bit Cluster thread scheme ID override register.
CLUSTERPM* cp15 c15 0 or 6 c5-c6 0-7 32-bit or 64-bit Cluster PMU registers.

Legacy feature registers

Name Type Description
FCSEIDR RO

B1.46 FCSEIDR, FCSE Process ID Register

In Armv8‑A, the core does not implement the FCSEIDR, and therefore the register is RO.

Address registers

Name Type Description
PAR RW

B1.78 PAR, Physical Address Register

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