A1.1 About the core

The Cortex®-A55 core is a mid-range, low-power core that implements the Arm®v8‑A architecture with support for the Armv8.1‑A extension, the Armv8.2‑A extension, the RAS extension, the Load acquire (LDAPR) instructions introduced in the Armv8.3‑A extension, and the dot product instructions introduced in the Armv8.4‑A extension.

The core has a Level 1 (L1) memory system, and private Level 2 (L2) cache. The core is implemented inside the DynamIQ™ Shared Unit (DSU) as a Little core and is highly configurable with other cores.

The following figure shows an example of a dual-core configuration.

Figure A1-1 Example dual-core configuration with homogeneous cores
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The Cortex-A55 core can also be part of a heterogeneous system. The following figure shows an example in which the Cortex-A55 core and another core are integrated into a shared Level 3 (L3) cluster.

Figure A1-2 Example quad-core configuration with heterogeneous cores
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For more information on the permissible combination of cores in the cluster, see appendix Compatible Core Versions in the Arm® DynamIQ™ Shared Unit Configuration and Sign-off Guide.

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