B2.3 AArch64 implementation defined register summary

This section describes the AArch64 registers in the core that are implementation defined.

The following tables lists the AArch 64 implementation defined registers, sorted by opcode.

Table B2-3 AArch64 implementation defined registers

Name Op0 CRn Op1 CRm Op2 Width Description
AIDR_EL1 3 c0 1 c0 7 32 B2.14 AIDR_EL1, Auxiliary ID Register, EL1
ATCR_EL1 3 c15 0 c7 0 64 B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1
ATCR_EL2 3 c15 4 c7 0 64 B2.20 ATCR_EL2, Auxiliary Translation Control Register, EL2
ATCR_EL12 3 c15 5 c7 0 - B2.19 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1
ATCR_EL3 3 c15 6 c7 0 64 B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3
AVTCR_EL2 3 c15 4 c7 1 64 B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2
CCSIDR_EL1 3 c0 1 c0 0 32 B2.23 CCSIDR_EL1, Cache Size ID Register, EL1
CLIDR_EL1 3 c0 1 c0 1 64 B2.24 CLIDR_EL1, Cache Level ID Register, EL1
CPUACTLR_EL1 3 c15 0 c1 0 64 B2.28 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
CPUCFR_EL1 3 c15 0 c0 0 32 B2.29 CPUCFR_EL1, CPU Configuration Register, EL1
CPUECTLR_EL1 3 c15 0 c1 4 64 B2.30 CPUECTLR_EL1, CPU Extended Control Register, EL1
CPUPCR_EL3 3 15 6 c8 1 64 B2.31 CPUPCR_EL3, CPU Private Control Register, EL3
CPUPMR_EL3 3 c15 6 c8 3 64 B2.32 CPUPMR_EL3, CPU Private Mask Register, EL3
CPUPOR_EL3 3 c15 6 c8 2 64 B2.33 CPUPOR_EL3, CPU Private Operation Register, EL3
CPUPSELR_EL3 3 c15 6 c8 0 32 B2.34 CPUPSELR_EL3, CPU Private Selection Register, EL3
CPUPWRCTLR_EL1 3 c15 0 c2 7 32 B2.35 CPUPWRCTLR_EL1, Power Control Register, EL1
ERRIDR_EL1 3 c5 0 c3 0 32 B2.40 ERRIDR_EL1, Error ID Register, EL1
ERXPFGCDNR_EL1 3 c15 0 c2 2 32 B2.47 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
ERXPFGCTLR_EL1 3 c15 0 c2 1 32 B2.48 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
ERXPFGFR_EL1 3 c15 0 c2 0 32 B2.49 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1

The following table shows the 32-bit wide implementation defined Cluster registers. Details of these registers can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual

Table B2-4 Cluster registers

Name Op0 CRn op1 CRm op2 Width Description
CLUSTERCFR_EL1 3 c15 0 c3 0 32-bit Cluster configuration register.
CLUSTERIDR_EL1 3 c15 0 c3 1 32-bit Cluster main revision ID.
CLUSTEREVIDR_EL1 3 c15 0 c3 2 32-bit Cluster ECO ID.
CLUSTERACTLR_EL1 3 c15 0 c3 3 32-bit Cluster auxiliary control register.
CLUSTERECTLR_EL1 3 c15 0 c3 4 32-bit Cluster extended control register.
CLUSTERPWRCTLR_EL1 3 c15 0 c3 5 32-bit Cluster power control register.
CLUSTERPWRDN_EL1 3 c15 0 c3 6 32-bit Cluster power down register.
CLUSTERPWRSTAT_EL1 3 c15 0 c3 7 32-bit Cluster power status register.
CLUSTERTHREADSID_EL1 3 c15 0 c4 0 32-bit Cluster thread scheme ID register.
CLUSTERACPSID_EL1 3 c15 0 c4 1 32-bit Cluster ACP scheme ID register.
CLUSTERSTASHSID_EL1 3 c15 0 c4 2 32-bit Cluster stash scheme ID register.
CLUSTERPARTCR_EL1 3 c15 0 c4 3 32-bit Cluster partition control register.
CLUSTERBUSQOS_EL1 3 c15 0 c4 4 32-bit Cluster bus QoS control register.
CLUSTERL3HIT_EL1 3 c15 0 c4 5 32-bit Cluster L3 hit counter register.
CLUSTERL3MISS_EL1 3 c15 0 c4 6 32-bit Cluster L3 miss counter register.
CLUSTERTHREADSIDOVR_EL1 3 c15 0 c4 7 32-bit Cluster thread scheme ID override register.
CLUSTERPM*_ELx 3 c15 0 or 6 c5-c6 0-7 32-bit or 64-bit Cluster PMU registers
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