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The ID_ISAR6 provides information about the instruction sets that the core implements.
ID_ISAR6 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
UDOT and SDOT instructions. The value is:
|UDOT and SDOT instructions are implemented.|
ID_ISAR6 is architecturally mapped to AArch64 register ID_ISAR6_EL1. See B2.73 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR6 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. See:
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.