B1.39 ERXMISC1, Selected Error Miscellaneous Register 1

Register ERXMISC1 accesses bits [63:32] of the ERR<n>MISC0 miscellaneous register 0 for the error record selected by ERRSELR.SEL.

If ERRSELR.SEL==0, then ERXMISC1 accesses the ERR0MISC0[63:32] register of the core error record. See B3.5 ERR0MISC0, Error Record Miscellaneous Register 0.

If ERRSELR.SEL==1, then ERXMISC1 accesses the ERR1MISC0[63:32] register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

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