B1.8 AHTCR, Auxiliary Hypervisor Translation Control Register

The AHTCR determines the values of the Page Based Hardware Attribute (PBHA) on page table walks memory access in hypervisor translation regime.

Bit field descriptions

AHTCR is a 32-bit register.

Figure B1-4 AHTCR bit assignments
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[31:10]
RES0.
HWVAL60, [9]
Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set.
HWVAL59, [8]
Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set.
[7:2]
RES0.
HWEN60, [1]
Enables PBHA[1] page table walks memory access. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN59, [0]
Enables PBHA[0] page table walks memory access. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch32 register AHTCR is mapped to AArch64 register TCR_EL2.

Usage constraints

Accessing the AHTCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>
<Syntax> Coproc opc1 CRn CRm opc2
p15, 4, <Rt> , c15, c7, 0 1111 100 1111 0111 000
Accessibility

AHTCR is accessible as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 4, <Rt>, c15, c7, 0 x x 0 - - n/a RW
p15, 4, <Rt>, c15, c7, 0 x 0 1 - - RW RW
p15, 4, <Rt>, c15, c7, 0 x 1 1 - n/a RW RW
Traps and enables
The traps and enables that apply to this register are the same traps and enables that apply to HTCR.
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