B2.108 VSESR_EL2, Virtual SError Exception Syndrome Register

The VSESR_EL2 provides the syndrome value reported to software on taking a virtual SError interrupt exception.

Bit field descriptions

VSESR_EL2 is a 64-bit register, and is part of :

  • The Exception and fault handling registers functional group.
  • The The Virtualization registers functional group.

The register has two bit assignment configurations, that depend on whether the virtual SError interrupt is taken to EL1 using AArch32 or AArch64:

  • If the virtual SError interrupt is taken to EL1 using AArch64, VSESR_EL2 provides the syndrome value reported in ESR_EL1.
  • If the virtual SError interrupt is taken to EL1 using AArch32, VSESR_EL2 provides the syndrome values reported in DFSR bits

VSESR_EL2 bit assignments when EL1 is using AArch32

Figure B2-97 VSESR_EL2 bit assignments when EL1 is using AArch32
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RES0, [63:16]
RES0Reserved.
AET, [15:14]

Asynchronous Error Type. Describes the state of the core after taking the SError interrupt exception. Software might use the information in the syndrome registers to determine what recovery might be possible.

RES0, [13:0]
RES0Reserved.

VSESR_EL2 bit assignments when EL1 is using AArch64

Figure B2-98 VSESR_EL2 bit assignments when EL1 is using AArch64
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RES0, [63:25]
RES0Reserved.
IDS, [24]

Indicates whether the deferred SError interrupt was of an IMPLEMENTATION DEFINED type. See ESR_EL1.IDS for a description of the functionality.

On taking a virtual SError interrupt to EL1 using AArch64 due to HCR_EL2.VSE == 1, ESR_EL1[24] is set to VSESR_EL2.IDS.

ISS, [23:0]

Syndrome information.See ESR_EL1.ISS for a description of the functionality.

On taking a virtual SError interrupt to EL1 using AArch32 due to HCR_EL2.VSE == 1, ESR_EL1 [23:0] is set to VSESR_EL2.ISS.

Configurations

AArch64 System register VSESR_EL2 [31:0] is architecturally mapped to AArch32 System register VDFSR. See B1.87 VDFSR, Virtual SError Exception Syndrome Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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