B3.5 ERR0MISC0, Error Record Miscellaneous Register 0

The ERR0MISC0 is an error syndrome register. It contains corrected error counters, information to identify where the error was detected, and other state information not present in the corresponding status and address error record registers.

Bit field descriptions

ERR0MISC0 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

Figure B3-3 ERR0MISC0 bit assignments
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RES0, [63:47]
RES0Reserved.
OFO, [47]

Other Error Count Overflow.

Set when the other error count field overflows. The fault handling interrupt will be asserted when this bit is set and the corrected fault handling interrupt is enabled.

CECO, [46:40]

Other Error Count.

This field is incremented on any corrected memory error that does not match the location (set/way/level/cache/etc) information in this register.

OFR, [39]

Repeat Error Count Overflow.

Set when the repeat error count field overflows. The fault handling interrupt will be asserted when this bit is set and the corrected fault handling interrupt is enabled.

CECR, [38:32]

Repeat Error Count.

This field is incremented on any corrected memory error that exactly matches the location (set/way/level/cache/etc) information in this register.

WAY, [31:28]

Indicates the way that contained the error.

  • For all RAMs in the core, only bits [31:30] are used.
  • For the L1 instruction cache RAMs, this indicates the RAM bank rather than the way.
RES0, [27:19]
RES0Reserved.
INDX, [18:6]

Indicates the index that contained the error.

Upper bits of the index are unused depending on the cache size.

RES0, [5:4]
RES0Reserved.
LVL, [3:1]
Indicates the level that contained the error. The possible values are:
0b000Level 1.
0b001Level 2.
IND, [0]
Indicates the type of cache that contained the error. The possible values are:
0L1 data cache, unified L2 cache, or TLB.
1L1 instruction cache.
Configurations
ERR0MISC0 resets to 0x0000000000000000.
This register is accessible from the following registers when ERRSELR.SEL==0:
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