B1.58 HTTBR, Hyp Translation Table Base Register

The HTTBR holds the base address of the translation table for the stage 1 translation of memory accesses from Hyp mode.

Bit field descriptions

HTTBR is a 64-bit register.

Figure B1-43 HTTBR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

CnP, [0]
Common not Private. The possible values are:
0CnP is not supported.
1CnP is supported.

AArch32 System register HTTBR is architecturally mapped to AArch64 System register TTBR0_EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.