|Home > Register Descriptions > AArch32 system registers > HTTBR, Hyp Translation Table Base Register|
The HTTBR holds the base address of the translation table for the stage 1 translation of memory accesses from Hyp mode.
HTTBR is a 64-bit register.
|0||CnP is not supported.|
|1||CnP is supported.|
AArch32 System register HTTBR is architecturally mapped to AArch64 System register TTBR0_EL2.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.