B3.3 ERR0CTLR, Error Record Control Register

The ERR0CTLR contains enable bits for the node that write to this record:

  • Enabling error detection and correction.
  • Enabling an error recovery interrupt.
  • Enabling a fault handling interrupt.
  • Enabling error recovery reporting as a read or write error response.

Bit field descriptions

ERR0CTLR is a 64-bit register and is part of the RAS registers functional group.

Figure B3-1 ERR0CTLR bit assignments
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RES0, [63:9]
RES0Reserved.
CFI, [8]

Fault handling interrupt for corrected errors enable. The fault handling interrupt is generated when one of the standard CE counters on ERR0MISC0 overflows and the overflow bit is set. The possible values are:

0Fault handling interrupt not generated for corrected errors.
1Fault handling interrupt generated for corrected errors.

The interrupt is generated even if the error status is overwritten because the error record already records a higher priority error. If the node does not support this control, this bit is RES0.

Note:

This control applies to both reads and writes.
RES0, [7:4]
RES0Reserved.
FI, [3]

Fault handling interrupt enable.

The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors. The possible values are:

0Fault handling interrupt disabled.
1Fault handling interrupt enabled.
UI, [2]

Uncorrected error recovery interrupt enable. When enabled, the error recovery interrupt is generated for all detected Uncorrected errors that are not deferred. The possible values are:

0Error recovery interrupt disabled.
1Error recovery interrupt enabled.

Note:

Applies to both reads and writes.
RES0, [1]
RES0Reserved.
ED, [0]

Enable error detection. When disabled, error detection and correction is disabled on reads. Error correction codes are still written for writes. The possible values are:

0Error detection and correction disabled.
1Error detection and correction enabled.

Note:

The bit is set to 0 on Cold reset, meaning errors are not detected or corrected from Cold reset. This allows boot software to initialize the core without signaling errors. When the node is initialized, software can enable error detection.
Configurations
ERR0CTLR resets to 0x0000000000000000.
This register is accessible from the following registers when ERRSELR.SEL==0:
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