B3.3 ERR0CTLR, Error Record Control Register
The ERR0CTLR contains enable bits for the node that write to this record:
- Enabling error detection and correction.
- Enabling an error recovery interrupt.
- Enabling a fault handling interrupt.
- Enabling error recovery reporting as a read or write error response.
Bit field descriptions
ERR0CTLR is a 64-bit register and is part of the RAS registers functional
B3-1 ERR0CTLR bit assignments
- RES0, [63:9]
- CFI, 
Fault handling interrupt for corrected errors enable.
The fault handling interrupt is generated when one of the standard CE
counters on ERR0MISC0 overflows and the overflow bit is set. The
possible values are:
|Fault handling interrupt not generated for
|Fault handling interrupt generated for
The interrupt is generated even if the error status is
overwritten because the error record already records a higher priority
error. If the node does not support this control, this bit is RES0.
Note: This control applies to both reads and writes.
- RES0, [7:4]
- FI, 
Fault handling interrupt enable.
The fault handling interrupt is generated for all detected Deferred errors
and Uncorrected errors. The possible values are:
|Fault handling interrupt disabled.
|Fault handling interrupt enabled.
- UI, 
Uncorrected error recovery interrupt enable. When enabled, the error
recovery interrupt is generated for all detected Uncorrected errors that
are not deferred. The possible values are:
|Error recovery interrupt disabled.
|Error recovery interrupt enabled.
Note: Applies to both reads and writes.
- RES0, 
- ED, 
Enable error detection. When disabled, error detection and correction is
disabled on reads. Error correction codes are still written for writes.
The possible values are:
|Error detection and correction disabled.
|Error detection and correction enabled.
Note: The bit is set to 0 on Cold reset, meaning errors are
not detected or corrected from Cold reset. This allows boot software to
initialize the core without signaling errors. When the node is
initialized, software can enable error detection.
- ERR0CTLR resets to
- This register is accessible from the following registers when