A3.1 About clocks, resets, and input synchronization

The Cortex®-A55 core supports hierarchical clock gating.

The Cortex-A55 core contains several interfaces that connect to other components in the system. These interfaces can be in the same clock domain or in other clock domains.

For information about clocks, resets, and input synchronization, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.