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The first level of caching for the translation table information is an L1 TLB, implemented on each of the instruction and data sides.
The Cortex®-A55 L1 instruction TLB supports 4KB, 16KB, 64KB, and 2MB pages.
The Cortex-A55 L1 data TLB supports 4KB pages only.
Any other page sizes are fractured after the L2 TLB and the appropriate page size sent to the L1 TLB.
All TLB maintenance operations affect both the L1 instruction and data TLBs and cause them to be invalidated.