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The Intermediate Physical Address (IPA) cache RAM holds mappings between the IPAs and Physical Addresses (PAs).
Only Non-secure EL1 and EL0 stage 2 translations use the IPA cache. When a stage 2 translation completes, the cache is updated. The IPA cache is checked whenever a stage 2 translation is required.
Like the L2 TLB, the IPA cache RAM can hold entries for different sizes.