A5.3 TLB match process

The Arm®v8‑A architecture provides support for multiple maps from the VA space that are translated differently.

TLB entries store the context information that is required to facilitate a match and avoid the need for a TLB flush on a context or virtual machine switch.

Each TLB entry contains a:

  • VA.
  • PA.
  • Set of memory properties that include type and access permissions.

Each entry is either associated with a particular Address Space Identifier (ASID) or is global. In addition, each TLB entry contains a field to store the Virtual Machine Identifier (VMID) in the entry applicable to accesses from Non-secure EL0 and EL1 Exception levels.

Each entry is associated with a particular translation regime.

  • EL3 in Secure state in AArch64 only.
  • EL2 (or EL0 in VHE mode) in Non-secure state.
  • EL1 or EL0 in Secure state or EL3 in Secure state in AArch32.
  • EL1 or EL0 in Non-secure state.

A TLB match entry occurs when the following conditions are met:

  • When VA[48:N] matches the requested address, where N is log2 of the block size for that translation that is stored in the TLB entry, moderated by the page size.
  • When the memory space matches the memory space state of the requests. The memory space can be one of the four states mentioned above.
  • The ASID matches the current ASID held in the CONTEXTIDR, TTBR0, or TTBR1 register, or the entry is marked global.
  • The ASID matches are ignored for requests originating from EL2 when not in VHE mode or from EL3 in AArch64.
  • The VMID matches the current VMID held in the VTTBR_EL2 register.
  • The VMID match is ignored for a request not originating from Non-secure EL0 or EL1.
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