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The Arm®v8‑A architecture provides support for multiple maps from the VA space that are translated differently.
TLB entries store the context information that is required to facilitate a match and avoid the need for a TLB flush on a context or virtual machine switch.
Each TLB entry contains a:
Each entry is either associated with a particular Address Space Identifier (ASID) or is global. In addition, each TLB entry contains a field to store the Virtual Machine Identifier (VMID) in the entry applicable to accesses from Non-secure EL0 and EL1 Exception levels.
Each entry is associated with a particular translation regime.
A TLB match entry occurs when the following conditions are met: