A6.1 About the L1 memory system

The L1 memory system enhances the performance and power efficiency in the Cortex®-A55 core.

It consists of separate instruction and data caches. You can configure instruction and data caches independently during implementation to sizes of 16KB, 32KB, or 64KB.

L1 instruction-side memory system

The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:

  • 64-byte instruction side cache line length.
  • 4-way set associative L1 instruction cache.
  • 128-bit read interface to the L2 memory system.

The Cortex-A55 core uses extensive branch prediction to improve Instructions Per Clock (IPC) and power efficiency.

L1 data-side memory system

The L1 data-side memory system responds to load and store requests from the DPU. It also responds to SCU snoop requests from other cores, or external masters. Its key features are:

  • 64-byte data side cache line length.
  • 4-way set associative L1 data cache.
  • Read buffer that services both the Data Cache Unit (DCU), and the Instruction Fetch Unit (IFU).
  • 64-bit read path from the data L1 memory system to the datapath.
  • 128-bit write path from the datapath to the L1 memory system.
  • Merging store buffer capability which writes to all types of memory (device, normal cacheable and normal non-cacheable).
  • Data side prefetch engine that detects patterns of strides with multiple streams are allowed in parallel, capable of detecting both constant and patterns of strides.
Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.