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The L1 memory system enhances the performance and power efficiency in the Cortex®-A55 core.
It consists of separate instruction and data caches. You can configure instruction and data caches independently during implementation to sizes of 16KB, 32KB, or 64KB.
The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are:
The Cortex-A55 core uses extensive branch prediction to improve Instructions Per Clock (IPC) and power efficiency.
The L1 data-side memory system responds to load and store requests from the DPU. It also responds to SCU snoop requests from other cores, or external masters. Its key features are: