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The Cortex®-A55 core uses the MESI protocol to maintain data coherency between multiple cores.
MESI describes the state that a shareable line in a L1 data cache can be in:
|M||Modified/UniqueDirty (UD). The line is in only this cache and is dirty.|
|E||Exclusive/UniqueClean (UC). The line is in only this cache and is clean.|
|S||Shared/SharedClean (SC). The line is possibly in more than one cache and is clean.|
|I||Invalid/Invalid (I). The line is not in this cache.|
The DCU stores the MESI state of the cache line in the tag and dirty RAMs.