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The Cortex®-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system.
The L2 cache controller handles requests from the L1 instruction and data caches, and snoop requests from the L3 memory system. The L2 memory system forwards responses from the L3 system to the core, which can then take precise or imprecise aborts, depending on the type of transaction.
The L2 memory subsystem consists of:
The main features of the L2 memory system are: