A8.7 Error injection

To support testing of error handling software, the Cortex®-A55 core can fake errors in the error detection logic.

The following table describes the possible types of errors that the core can encounter and therefore fake.

Table A8-2 Errors injected in the Cortex-A55 core

Error type Description
Corrected errors A CE is generated for a single ECC error on L1 data cache access.
Deferred errors A DE is generated for a double ECC error on eviction of a cache line from the L1 to the L2, or as a result of a snoop on the L1.
Uncontainable errors A UC is generated for a double ECC error on the L1 TAG RAM following an eviction.
Latent error A UEO is generated as a double ECC error on an L1 data read.

The following table describes the registers that handle error injection in the Cortex-A55 core.

Table A8-3 Error injection registers

Register name Description
ERR<n>PFGFR The ERR Pseudo Fault Generation Feature register defines which errors can be injected.
ERR<n>PFGCTLR The ERR Pseudo Fault Generation Control register controls the errors that are injected.
ERXPFGCDN_EL1 The Selected Pseudo Fault Generation Count Down register controls the fault injection timing.

Note:

This mechanism simulates the corruption of any RAM but the data is not corrupted.
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