C1.3.2 Effects of resets on debug registers
The core has the following reset signals that affect the debug registers:
- This signal initializes the core logic, including the debug, ETM
trace unit, breakpoint, watchpoint logic, and performance monitors logic. This maps to a
Cold reset that covers reset of the core logic and the integrated debug
- This signal resets some of the debug and performance monitor logic.
This maps to a Warm reset that covers reset of the core logic.
- This signal initializes the shared debug APB, CTI, and CTM logic. This
maps to an External Debug reset that covers the resetting of the external debug
interface and has no impact on the core functionality.