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External access permission to the debug registers is subject to the conditions at the time of the access.
The following table describes the core response to accesses through the external debug interface.
Table C1-1 External access conditions to registers
|Off||EDPRSR.PU is 0||
Core power domain is completely off, or in a low-power state where the core power domain registers cannot be accessed.
If debug power is off, then all external debug and memory-mapped register accesses return an error.
||OS Double Lock is locked.|
|OSLK||OSLSR_EL1.OSLK is 1||OS Lock is locked.|
||External debug access is disabled. When an error is returned because of an EDAD condition code, and this is the highest priority error condition, EDPRSR.SDAD is set to 1. Otherwise SDAD is unchanged.|
|Default||-||None of the conditions apply, normal access.|
The following table shows an example of external register access condition codes for access to a performance monitor register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops.
Table C1-2 External register condition code example