B3.1 Error system register summary

The ERR0* registers are agnostic to the architectural state. For example, this means that for ERRSELR==0 and ERRSELR_EL1==0, ERXPFGFR and ERXPFGFR_EL1 will both access ERR0PFGFR.

For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The following table describes the architectural error record registers.

Table B3-1 Architectural error system register summary

Register mnemonic Size Register name Access aliases from AArch32 and AArch64
ERR0ADDR 64 B3.2 ERR0ADDR, Error Record Address Register B1.32 ERXADDR, Selected Error Record Address Register.
B1.33 ERXADDR2, Selected Error Record Address Register 2.
B2.42 ERXADDR_EL1, Selected Error Record Address Register, EL1
ERR0CTLR 64 B3.3 ERR0CTLR, Error Record Control Register B1.34 ERXCTLR, Selected Error Record Control Register.
B1.35 ERXCTLR2, Selected Error Record Control Register 2.
B2.43 ERXCTLR_EL1, Selected Error Record Control Register, EL1
ERR0FR 64 B3.4 ERR0FR, Error Record Feature Register B1.36 ERXFR, Selected Error Record Feature Register.
B1.37 ERXFR2, Selected Error Record Feature Register 2.
B2.44 ERXFR_EL1, Selected Error Record Feature Register, EL1
ERR0MISC0 64 B3.5 ERR0MISC0, Error Record Miscellaneous Register 0 B1.38 ERXMISC0, Selected Error Miscellaneous Register 0 .
B1.39 ERXMISC1, Selected Error Miscellaneous Register 1.
B2.45 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
ERR0MISC1 64 B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 B1.40 ERXMISC2, Selected Error Record Miscellaneous Register 2 accesses bits [31:0]
B1.41 ERXMISC3, Selected Error Record Miscellaneous Register 3 accesses bits [63:32]
B2.46 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
ERR0STATUS 32 B3.10 ERR0STATUS, Error Record Primary Status Register B1.45 ERXSTATUS, Selected Error Record Primary Status Register
B2.50 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1

The following table describes the error record registers that are IMPLEMENTATION DEFINED.

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