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In the Cortex®-A55 core, watchpoint debug events are always synchronous.
Memory hint instructions and cache clean operations, except
DC IVAC, and
DCIMVAC, do not generate watchpoint debug events. Store exclusive
instructions generate a watchpoint debug event even when the check for the control of
exclusive monitor fails. Atomic CAS instructions generate a watchpoint debug event even when
the compare operation fails.
For watchpoint debug events, except those resulting from cache maintenance operations, the value reported in DFAR is guaranteed to be no lower than the address of the watchpoint location rounded down to a multiple of 16 bytes.