C2.2 PMU functional description
This section describes the functionality of the PMU.
The PMU includes the following interfaces and counters:
- Event interface
- Events from all other units from across the design are provided to the PMU.
- System register and APB interface
- You can program the PMU registers using the system registers or the external APB
- The PMU has 32-bit counters that increment when they are enabled, based on events, and
a 64-bit cycle counter.
- PMU register interfaces
- The Cortex®-A55 core supports access to
the performance monitor registers from the internal system register interface and a