|Home > Debug descriptions > PMU > External register access permissions to the PMU registers|
External access permission to the PMU registers is subject to the conditions at the time of the access.
The following table describes the core response to accesses through the external debug and memory-mapped interfaces.
Table C2-1 External register conditions
|Off||EDPRSR.PU is 0||
Core power domain is completely off, or in a low-power state where the core power domain registers cannot be accessed.
|DLK||EDPRSR.DLK is 1||OS Double Lock is locked.|
|OSLK||OSLSR_EL1.OSLK is 1||OS Lock is locked.|
||External performance monitors access is disabled. When an error is returned because of an EPMAD condition code, and this is the highest priority error condition, EDPRSR.SPMAD is set to 1. Otherwise SPMAD is unchanged.|
|Default||-||None of the conditions apply, normal access.|
The following table shows an example of external register condition codes for access to a performance monitor register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column whose condition is true, the entry gives the register access permission and scanning stops.
Table C2-2 External register condition code example