B.1 Revisions

This appendix describes the technical changes between released issues of this book.

Table B-1 Issue 0000-00

Change Location Affects

First release

- -

Table B-2 Differences between issue 0000-00 and issue 0001-00

Change Location Affects

Editorial changes

- r0p1

Updated the product revision to r0p1

- r0p1

Minor updates in the components section

A2.1 Components r0p1

Added a set of timer registers

A2.4 About the Generic Timer r0p1

Updated the core dynamic retention mode

A4.6.5 Core dynamic retention r0p1

Updated the section regarding configuring MMU accesses

A5.5.1 Configuring MMU accesses r0p1

Updated the section regarding external aborts

A5.6.3 External aborts r0p1

Updated the section regarding mis-programming contiguous hints

A5.6.4 Mis-programming contiguous hints r0p1

Updated the section regarding conflict aborts

A5.6.5 Conflict aborts r0p1

Updated the direct access to internal memory

A6.6 Direct access to internal memory r0p1

Added information on outstanding simultaneous transactions supported

A7.1 About the L2 memory system r0p1

Updated the support for memory types section

A7.3 Support for memory types r0p1

Updated the cluster registers tables

B1.3 AArch32 implementation defined register summary, B1.4 AArch32 registers by functional group, B2.3 AArch64 implementation defined register summary, B2.4 AArch64 registers by functional group r0p1

Updated the ACTLR_EL2 register

B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 r0p1

Updated the ACTLR_EL3 register

B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 r0p1

Updated the IFSR32_EL2 register

B2.82 IFSR32_EL2, Instruction Fault Status Register, EL2 r0p1

Updated the VDISR_EL2 register at EL1 using AArch64

B2.105.3 VDISR_EL2 at EL1 using AArch64 r0p1

Updated the ERR0PFGCDNR register

B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register r0p1

Updated the ERR0PFGCTLR, register

B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register r0p1

Updated the PMU events

C2.4 PMU events r0p1

Table B-3 Differences between issue 0001-00 and issue 0100-00

Change Location Affects

Editorial changes.

- r1p0

Updated the product revision to r1p0.

- r1p0

Updated product name.

- r1p0

Global terminology change from 'processor' to 'core' for the product.

- r1p0

Updated FCM to DSU.

- r1p0

Added ELA address size option.

A1.3 Implementation options. r1p0

Updated the encoding for the L2 TLB.

A6.6.3 Encoding for the L2 TLB. r1p0

Added CPU private registers.

B1.3 AArch32 implementation defined register summary.

B1.4 AArch32 registers by functional group.

B1.21 CPUPCR, CPU Private Control Register.

B1.22 CPUPMR, CPU Private Mask Register.

B1.23 CPUPOR, CPU Private Operation Register.

B1.24 CPUPSELR, CPU Private Selection Register.

B2.3 AArch64 implementation defined register summary.

B2.4 AArch64 registers by functional group.

B2.31 CPUPCR_EL3, CPU Private Control Register, EL3.

B2.32 CPUPMR_EL3, CPU Private Mask Register, EL3.

B2.33 CPUPOR_EL3, CPU Private Operation Register, EL3.

B2.34 CPUPSELR_EL3, CPU Private Selection Register, EL3.

r1p0

Added dot product instructions introduced in Arm®v8.4‑A.

A1.3 Implementation options.

B1.2 AArch32 architectural system register summary.

B1.4 AArch32 registers by functional group.

B1.67 ID_ISAR6, Instruction Set Attribute Register 6.

B2.2 AArch64 architectural system register summary.

B2.4 AArch64 registers by functional group.

B2.73 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.

B2.58 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1.

r1p0

Updated the CPUECTLR and CPUECTLR_EL1 registers.

B1.20 CPUECTLR, CPU Extended Control Register.

B2.30 CPUECTLR_EL1, CPU Extended Control Register, EL1.

r1p0

Updated the Use of R15 by Instruction.

A.1 Use of R15 by Instruction. r1p0

Table B-4 Differences between issue 0100-00 and issue 0100-01

Change Location Affects

Updated company name to Arm

- r1p0

Updated the encoding for tag and data in the L1 data cache

A6.6.1 Encoding for tag and data in the L1 data cache r1p0

Updated the encoding for tag and data in the L1 instruction cache

A6.6.2 Encoding for tag and data in the L1 instruction cache r1p0

Updated the transient hit behavior

A7.3 Support for memory types r1p0

Updated the descriptions of bit[0] and bit[37] of the CPUECTLR register

B1.20 CPUECTLR, CPU Extended Control Register r1p0

Updated the traps and enables in the ERXPFGCDNR, ERXPFGCTLR, and ERXPFGFR registers

B1.42 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register, B1.43 ERXPFGCTLR, Selected Error Pseudo Fault Generation Control Register, and B1.44 ERXPFGFR, Selected Pseudo Fault Generation Feature Register r1p0

Table B-5 Differences between issue 0100-01 and issue 0200-00

Change Location Affects

Removed Dot Product instruction support as an implementation option

A1.3 Implementation options r2p0

Added PBHA support as an implementation option

A1.3 Implementation options and A5.7 Page Based Hardware Attributes r2p0

Updated transient memory region and non-temporal loads content

A6.4.1 Memory system implementation r2p0

Updated encoding for tag and data in the L1 data cache

A6.6.1 Encoding for tag and data in the L1 data cache r2p0

Updated main TLB RAM descriptor fields

A6.6.4 Main TLB RAM descriptor fields r2p0

Added AHTCR, ATTBCR, AVTCR registers

B1.3 AArch32 implementation defined register summary, B1.4 AArch32 registers by functional group, B1.8 AHTCR, Auxiliary Hypervisor Translation Control Register, B1.13 ATTBCR, Auxiliary Translation Table Base Control Register, and B1.14 AVTCR, Auxiliary Virtualized Translation Control Register r2p0

Updated MIDR register

B1.4 AArch32 registers by functional group and B1.76 MIDR, Main ID Register r2p0

Updated CCSIDR encodings to include 256KB and 8MB L3 cache

B1.15 CCSIDR, Cache Size ID Register r2p0

Added ATCR_EL1, ATCR_EL12, ATCR_EL2, ATCR_EL3, and AVTCR_EL2 registers

B2.3 AArch64 implementation defined register summary, B2.4 AArch64 registers by functional group, B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1, B2.19 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1, B2.20 ATCR_EL2, Auxiliary Translation Control Register, EL2, B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3, and B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2 r2p0

Updated MIDR_EL1 register

B2.4 AArch64 registers by functional group and B2.89 MIDR_EL1, Main ID Register, EL1 r2p0

Updated ID_AA64PFR0_EL1 register to include CSV2 and CSV3

B2.63 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 r2p0

Added ID_AA64PFR1_EL1 register

B2.64 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 r2p0

Updated ID_PFR0_EL1 register to include CSV2

B2.79 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 r2p0

Added ID_PFR2_EL1 register

B2.81 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1 r2p0

Updated EDPIDR2 register

D3.14 EDPIDR3, External Debug Peripheral Identification Register 3 r2p0

Updated the PMU common events

D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1 r2p0

Updated PMPIDR2 register

D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2 r2p0
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