Part D Debug registers

Table of Contents

D1 AArch32 Debug Registers
D1.1 AArch32 debug register summary
D1.2 DBGBCR, Debug Breakpoint Control Registers
D1.3 DBGDEVID, Debug Device ID Register
D1.4 DBGDEVID1, Debug Device ID Register 1
D1.5 DBGDIDR, Debug ID Register
D1.6 DBGWCR, Debug Watchpoint Control Registers
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
D2.5 MDSCR_EL1, Monitor Debug System Control Register, EL1
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
D3.2 EDCIDR0, External Debug Component Identification Register 0
D3.3 EDCIDR1, External Debug Component Identification Register 1
D3.4 EDCIDR2, External Debug Component Identification Register 2
D3.5 EDCIDR3, External Debug Component Identification Register 3
D3.6 EDDEVID, External Debug Device ID Register 0
D3.7 EDDEVID1, External Debug Device ID Register 1
D3.8 EDDFR, External Debug Feature Register
D3.9 EDITCTRL, External Debug Integration Mode Control Register
D3.10 EDPFR, External Debug Processor Feature Register
D3.11 EDPIDR0, External Debug Peripheral Identification Register 0
D3.12 EDPIDR1, External Debug Peripheral Identification Register 1
D3.13 EDPIDR2, External Debug Peripheral Identification Register 2
D3.14 EDPIDR3, External Debug Peripheral Identification Register 3
D3.15 EDPIDR4, External Debug Peripheral Identification Register 4
D3.16 EDPIDRn, External Debug Peripheral Identification Registers 5-7
D3.17 EDRCR, External Debug Reserve Control Register
D4 AArch32 PMU Registers
D4.1 AArch32 PMU register summary
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1
D4.4 PMCR, Performance Monitors Control Register
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
D6.2 PMCFGR, Performance Monitors Configuration Register
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7
D7 PMU snapshot registers
D7.1 PMU snapshot register summary
D7.2 PMPCSSR, Snapshot Program Counter Sample Register
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register
D7.5 PMSSSR, PMU Snapshot Status Register
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
D7.9 PMSSCR, PMU Snapshot Capture Register
D8 ETM registers
D8.1 ETM register summary
D8.2 TRCACATRn, Address Comparator Access Type Registers 0-7
D8.3 TRCACVRn, Address Comparator Value Registers 0-7
D8.4 TRCAUTHSTATUS, Authentication Status Register
D8.5 TRCAUXCTLR, Auxiliary Control Register
D8.6 TRCBBCTLR, Branch Broadcast Control Register
D8.7 TRCCCCTLR, Cycle Count Control Register
D8.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
D8.9 TRCCIDCVR0, Context ID Comparator Value Register 0
D8.10 TRCCIDR0, ETM Component Identification Register 0
D8.11 TRCCIDR1, ETM Component Identification Register 1
D8.12 TRCCIDR2, ETM Component Identification Register 2
D8.13 TRCCIDR3, ETM Component Identification Register 3
D8.14 TRCCLAIMCLR, Claim Tag Clear Register
D8.15 TRCCLAIMSET, Claim Tag Set Register
D8.16 TRCCNTCTLR0, Counter Control Register 0
D8.17 TRCCNTCTLR1, Counter Control Register 1
D8.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
D8.19 TRCCNTVRn, Counter Value Registers 0-1
D8.20 TRCCONFIGR, Trace Configuration Register
D8.21 TRCDEVAFF0, Device Affinity Register 0
D8.22 TRCDEVAFF1, Device Affinity Register 1
D8.23 TRCDEVARCH, Device Architecture Register
D8.24 TRCDEVID, Device ID Register
D8.25 TRCDEVTYPE, Device Type Register
D8.26 TRCEVENTCTL0R, Event Control 0 Register
D8.27 TRCEVENTCTL1R, Event Control 1 Register
D8.28 TRCEXTINSELR, External Input Select Register
D8.29 TRCIDR0, ID Register 0
D8.30 TRCIDR1, ID Register 1
D8.31 TRCIDR2, ID Register 2
D8.32 TRCIDR3, ID Register 3
D8.33 TRCIDR4, ID Register 4
D8.34 TRCIDR5, ID Register 5
D8.35 TRCIDR8, ID Register 8
D8.36 TRCIDR9, ID Register 9
D8.37 TRCIDR10, ID Register 10
D8.38 TRCIDR11, ID Register 11
D8.39 TRCIDR12, ID Register 12
D8.40 TRCIDR13, ID Register 13
D8.41 TRCIMSPEC0, Implementation Specific Register 0
D8.42 TRCITATBIDR, Integration ATB Identification Register
D8.43 TRCITCTRL, Integration Mode Control Register
D8.44 TRCITIATBINR, Integration Instruction ATB In Register
D8.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
D8.46 TRCITIDATAR, Integration Instruction ATB Data Register
D8.47 TRCLAR, Software Lock Access Register
D8.48 TRCLSR, Software Lock Status Register
D8.49 TRCCNTVRn, Counter Value Registers 0-1
D8.50 TRCOSLAR, OS Lock Access Register
D8.51 TRCOSLSR, OS Lock Status Register
D8.52 TRCPDCR, Power Down Control Register
D8.53 TRCPDSR, Power Down Status Register
D8.54 TRCPIDR0, ETM Peripheral Identification Register 0
D8.55 TRCPIDR1, ETM Peripheral Identification Register 1
D8.56 TRCPIDR2, ETM Peripheral Identification Register 2
D8.57 TRCPIDR3, ETM Peripheral Identification Register 3
D8.58 TRCPIDR4, ETM Peripheral Identification Register 4
D8.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
D8.60 TRCPRGCTLR, Programming Control Register
D8.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
D8.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
D8.63 TRCSEQRSTEVR, Sequencer Reset Control Register
D8.64 TRCSEQSTR, Sequencer State Register
D8.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
D8.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
D8.67 TRCSTALLCTLR, Stall Control Register
D8.68 TRCSTATR, Status Register
D8.69 TRCSYNCPR, Synchronization Period Register
D8.70 TRCTRACEIDR, Trace ID Register
D8.71 TRCTSCTLR, Global Timestamp Control Register
D8.72 TRCVICTLR, ViewInst Main Control Register
D8.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
D8.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
D8.75 TRCVMIDCVR0, VMID Comparator Value Register 0
D8.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0
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