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The following figure shows the supported modes for each core domain, and the legal transitions between them.
The darker (blue) blocks indicate the modes that the core can be initialized into. The dotted line transition from On to Core Dynamic Retention is only allowed if SIMD retention is not implemented or has been disabled.
The power domains can be controlled independently to give different combinations when powered-up and powered-down.
However, only some powered-up and powered-down domain combinations are valid and supported. The following table describes the power modes, and the corresponding supported power domain states for individual cores.
Table A4-2 Supported core power mode and power domain states
|Power mode||Power domain||Description|
|Debug recovery||On||On||Core on. Advanced SIMD and floating-point block on. Block is active.|
|On||On||On||Core on. Advanced SIMD and floating-point block on. Block is active.|
|SIMD dynamic retention||On||Ret||Core on. Advanced SIMD and floating-point block in retention. Block is active.|
|Core dynamic retention||Ret||Ret||Core retention. Core logic and Advanced SIMD and floating-point block in retention. Logic and RAM retention power only.|
|Off (emulated)||On||On||Core on. Advanced SIMD and floating-point block on. Block is active.|
|Off||Off||Off||Core off. Power to the block is gated.|
Deviating from the legal power modes can lead to unpredictable results. You must comply with the dynamic power management and powerup and powerdown sequences described in the following sections.