C1.2 Debug functional description

This section describes the trace, debug, and test features supported by Cortex®-A55. It includes Arm®v8‑A Debug, CoreSight™ Debug, and cache Debug.

Arm®v8‑A debug architecture support

The Cortex-A55 core supports the Armv8‑A debug architecture.

The core allows access to the internal debug functionality and registers either through a memory-mapped area on the external AMBA® APBv3 slave port, or by using CP14 system coprocessor operations from software running on the core.

The core implements six hardware breakpoints, four watchpoints, and a Debug Communications Channel (DCC). Four of the breakpoints match only against virtual address, the other two breakpoints match against either virtual address or context ID. All watchpoints can be linked to either of the virtual address or context-ID matching breakpoints to allow a memory request to be trapped in a given process context.

Note:

Armv7 debug map support
For backwards compatibility, and to reduce the address space required for the debug map, a 4k page-based memory map is also supported.

CoreSight debug

The Cortex-A55 core integrates several CoreSight debug related components to aid system debug in conjunction with CoreSight SoC.

These components include:

  • Per-core Embedded Trace Macrocell (ETM).
  • Per-core Cross Trigger Interface (CTI).
  • Cross Trigger Matrix (CTM).
  • Debug-over-power-down support.

The following figure shows the Cortex-A55 CoreSight debug components.

Note:

The DAP connection is shown for completeness.
Figure C1-2 Cortex-A55 debug components
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The debug components are split into two groups. Some components are in the cluster itself and the rest are in a separate block named the DebugBlock. It allows you to put the DebugBlock in a separate power domain and place it physically with other CoreSight logic in the SoC, rather than close to the cluster.

The connection between the cluster and the DebugBlock consists of a pair of APB interfaces, one in each direction. All debug traffic, except the authentication interface, takes place over this interface as read or write APB transactions. It includes register reads, writes, and CTI triggers.

All debug components are controlled through the primary Debug APB interface on the DebugBlock, and form a standard CoreSight interface. Requests on this bus are decoded by the APB decoder before being sent to the appropriate component in the DebugBlock or in the cluster. The per-core CTIs are connected to a CoreSight CTM.

Each core contains an ETM, PMU, and debug component that are accessed using the debug APB bus. This block conforms to the Armv8‑A Debug Architecture Specification.

The core supports debug-over-power-down using modules contained in the DebugBlock that mirror key core information such as core ID. These allow the JTAG scan chain connection to be maintained while the core is powered down.

The ETM in each core outputs trace on a 32-bit AMBA 4 ATBv1.1 interface. There is one interface per core.

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