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The Cortex®-A55 L1 data cache is a 4-way set associative structure.
The size of the configured cache determines the number of sets in each way.
The following table shows the encoding (set in
Rd in the appropriate
instruction) used to locate the cache data entry for tag and data memory. It is
similar for both the tag and data RAM access.
Data RAM access includes an extra field to locate the appropriate word in the cache line. The set-index range parameter (S) is:
|S=12||For a 16KB cache.|
|S=13||For a 32KB cache.|
|S=14||For a 64KB cache.|
Table A6-3 Cortex-A55 L1 Data Cache Tag and Data location encoding
|Bitfield of Rd||Description|
|[5:3]||Cache data element offset|
Tag information (MESI state, outer attributes, and valid) for the selected cache line, returns using Data Register 0 and Data Register 1.
Use the format that is shown in the following table.
Table A6-4 Cortex-A55 L1 Data Cache Tag data format
|Bitfield of Data Register 0 and 1||Description|
MESI State (from tag RAM):
|DR1||Non-secure state (NS) (from tag RAM)|
|DR1[28:1]||Tag Address [39:12] (from tag RAM)|
|DR0[6:5]||PBHA bits (from Dirty RAM)|
|DR0||Dirty bit (from Dirty RAM)|
|DR0||Shareability (from Dirty RAM)|
|DR0[2:1]||Age (from Dirty RAM)|
|DR0||Outer Allocation Hint (from Dirty RAM)|
The 64 bits of cache data returns in Data register 0 and Data register 1.