A6.6.3 Encoding for the L2 TLB

The Cortex®-A55 core L2 TLB is built from a 4-way set associative RAM-based structure and contains the data for the main TLB RAM, the Walk cache and IPA cache.

To read the individual entries into the data registers, software must write to the TLB Tag Read Operation Register and to the TLB Data Read Operation Register.

Table A6-7 Cortex-A55 TLB Data Read Operation Register location encoding

Bitfield of Rd Description
[31:30] TLB Way
[29:9] Unused
[8:0] TLB index

The TLB index is used to select the index from the TLB, walk cache, or IPA cache.

Table A6-8 TLB index

Bitfield of Rd Description
0x000-0FF Main TLB
0x100-10F Walk cache
0x110-11F IPA cache

The TLB uses an encoding for the descriptor that is returned using the following Data Registers:

Data Register 0[31:0]TLB Descriptor[31:0]
Data Register 1[31:0]TLB Descriptor[63:32]
Data Register 2[31:0]TLB Descriptor[88:64]
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