|Home > Register Descriptions > AArch64 system registers > ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1|
The ID_MMFR4_EL1 provides information about the memory model and memory management support in AArch32.
ID_MMFR4_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
|LSMAOE and nTLSMD bit not supported.|
Presence of Hierarchical Disables. Enables an operating system or hypervisor to hand over up to 4 bits of the last level page table descriptor (bits[62:59] of the page table entry) for use by hardware for IMPLEMENTATION DEFINED usage. The value is:
Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported.
|CnP bit supported.|
|EL0/EL1 execute control distinction at stage2 bit supported.|
|ACTLR2 and HACTLR2 are implemented.|
|The core never generates an SError interrupt due to an external abort on a speculative read.|
ID_MMFR4_EL1 is architecturally mapped to AArch64 register ID_MMFR4. See B1.72 ID_MMFR4, Memory Model Feature Register 4.
There is one copy of this register that is used in both Secure and Non-secure states.
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and ID_MMFR3_EL1. See:
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.