B2.61 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1

The ID_AA64MMFR1_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.

Bit field descriptions

ID_AA64MMFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-47 ID_AA64MMFR1_EL1 bit assignments
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RES0, [63:32]
XNX, [31:28]

Indicates whether provision of EL0 vs EL1 execute never control at Stage 2 is supported.

0x1EL0/EL1 execute control distinction at Stage 2 bit is supported. All other values are reserved.
RES0, [27:24]
PAN, [23:20]

Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0.

0x2PAN supported and AT S1E1RP and AT S1E1WP instructions supported.
LO, [19:16]

Indicates support for LORegions.

LORegions are supported.
HD, [15:12]

Presence of Hierarchical Disables. Enables an operating system or hypervisor to hand over up to 4 bits of the last level page table descriptor (bits[62:59] of the page table entry) for use by hardware for IMPLEMENTATION DEFINED usage. The value is:


Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported.

VH, [11:8]

Indicates whether Virtualization Host Extensions are supported.

0x1Virtualization Host Extensions supported.
VMID, [7:4]

Indicates the number of VMID bits supported.

0x216 bits are supported.
HAFDBS, [3:0]

Indicates the support for hardware updates to Access flag and dirty state in translation tables.

0x2Hardware update of both the Access flag and dirty state is supported in hardware.

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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