B1.31 ERRSELR, Error Record Select Register

The ERRSELR selects which error record should be accessed through the Error Record system registers. This register is not reset on a warm reset.

Bit field descriptions

ERRSELR is a 32-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

Figure B1-30 ERRSELR bit assignments
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RES0, [31:1]
RES0Reserved.
SEL, [0]
Selects the record accessed through the Error Record system registers.
0

Select record 0 containing errors from level-1 and level-2 RAMs located in the Cortex®-A55 core.

1

Select record 1 containing errors from level-3 RAMs located in the DSU.

Configurations

ERRSELR is architecturally mapped to AArch64 register ERRSELR_EL1. See B2.41 ERRSELR_EL1, Error Record Select Register, EL1 .

There is one copy of this register that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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