B2.41 ERRSELR_EL1, Error Record Select Register, EL1

The ERRSELR_EL1 selects which error record should be accessed through the Error Record system registers. This register is not reset on a warm reset.

Bit field descriptions

ERRSELR_EL1 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

Figure B2-36 ERRSELR_EL1 bit assignments
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RES0, [63:1]

Reserved,RES0.

SEL, [0]
Selects which error record should be accessed.
0

Select record 0 containing errors from Level 1 and Level 2 RAMs located on the Cortex®-A55 core.

1

Select record 1 containing errors from Level 3 RAMs located on the DSU.

Configurations

ERRSELR_EL1 is architecturally mapped to AArch32 register ERRSELR. See B1.31 ERRSELR, Error Record Select Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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