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The ERRIDR defines the number of error records that can be accessed through the Error Record system registers.
ERRIDR is a 32-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.
This register is Read Only.
Number of records that can be accessed through the Error Record system registers.
Two records present.
ERRIDR is architecturally mapped to AArch64 register ERRIDR_EL1. See B2.40 ERRIDR_EL1, Error ID Register, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.