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The ERRIDR_EL1 defines the number of error record registers.
ERRIDR_EL1 is a 32-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS) functional group.
This register is Read Only.
Number of records that can be accessed through the Error Record system registers.
Two records present.
ERRIDR_EL1 is architecturally mapped to AArch32 register ERRIDR. See B1.30 ERRIDR, Error ID Register.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.