B1.25 CPUPWRCTLR, CPU Power Control Register

The CPUPWRCTLR is a configuration register that gives indications to the external power controller.

Bit field descriptions

CPUPWRCTLR is a 32-bit register, and is part of the Implementation registers functional group.

Figure B1-21 CPUPWRCTLR bit assignments
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RES0, [31:13]
res0Reserved.
SIMD_RET_CTRL, [12:10]

Advanced SIMD and floating-point retention control:

0b000Disable the retention circuit. This is the default value, see Table   B2-7 CPUPWRCTLR Retention Control Field for more retention control options.
WFE_RET_CTRL, [9:7]

CPU WFE retention control:

0b000Disable the retention circuit. This is the default value, see Table   B1-7 CPUPWRCTLR Retention Control Field for more retention control options.
WFI_RET_CTRL, [6:4]

CPU WFI retention control:

0b000Disable the retention circuit. This is the default value, see Table   B1-7 CPUPWRCTLR Retention Control Field for more retention control options.
RES0, [3:1]
RES0Reserved.
CORE_PWRDN_EN, [0]

Indicates to the power controller if the CPU wants to power down when it enters WFI state.

0b0No power down requested.
0b1A power down is requested.

Table B1-7 CPUPWRCTLR Retention Control Field

Encoding Note

Minimum Delay before retention

50MHz – 10MHz
000 Disable the retention circuit. Default Condition.
001 2 Architectural Timer ticks are required before retention entry. 40ns – 200ns
010 8 Architectural Timer ticks are required before retention entry. 160ns – 800ns
011 32 Architectural Timer ticks are required before retention entry. 640ns – 3,200ns
100 64 Architectural Timer ticks are required before retention entry. 1,280ns – 6,400ns
101 128 Architectural Timer ticks are required before retention entry. 2,560ns – 12,800ns
110 256 Architectural Timer ticks are required before retention entry. 5,120ns – 25,600ns
111 512 Architectural Timer ticks are required before retention entry. 10,240ns – 51,200ns
Configurations

CPUPWRCTLR is architecturally mapped to AArch64 register CPUPWRCTLR_EL1. See B2.35 CPUPWRCTLR_EL1, Power Control Register, EL1.

Usage constraints

Accessing the CPUPWRCTLR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRn CRm opc2
p15, 0, <Rt>, c15, c2, 7 1111 000 1111 0010 111
Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 0, <Rt>, c15, c2, 7 x x 0 - RW n/a RW
p15, 0, <Rt>, c15, c2, 7 x 0 1 - RW RW RW
p15, 0, <Rt>, c15, c2, 7 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state.

Write access to this register from EL1 or EL2 depends on the value of bit[7] of ACTLR_EL2, ACTLR_EL3, ACTLR (S), and HACTLR.

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