B1.44 ERXPFGFR, Selected Pseudo Fault Generation Feature Register

Register ERXPFGFR accesses bits [31:0] of the ERR<n>PFGFR register for the error record selected by ERRSELR.SEL.

If ERRSELR.SEL==0, then ERXPFGFR accesses the ERR0PFGFR register of the core error record. See B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register.

If ERRSELR.SEL==1, then ERXPFGFR accesses the ERR1PFGFR register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.


ERXPFGFR is architecturally mapped to AArch64 register ERXPFGFR_EL1. See B2.49 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1.

Accessing the ERXPFGFR

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRn CRm opc2
p15, 0, <Rt>, c15, c2, 0 1111 000 1111 0010 000

This register is accessible in software as follows:

<syntax> Control Accessibility
p15, 0, <Rt>, c15, c2, 0 x x 0 - RO n/a RO
p15, 0, <Rt>, c15, c2, 0 x 0 1 - RO RO RO
p15, 0, <Rt>, c15, c2, 0 x 1 1 - n/a RO RO

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are applicable when accessing this register.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.