B1.42 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register

Register ERXPFGCDNR accesses the ERR<n>PFGCNDR register for the error record selected by ERRSELR.SEL.

If ERRSELR.SEL==0, then ERXPFGCDNR accesses the ERR0PFGCDNR register of the core error record. See B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register.

If ERRSELR.SEL==1, then ERXPFGCDNR accesses the ERR1PFGCDNR register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

Configurations

ERXPFGCDNR is architecturally mapped to AArch64 register ERXPFGCDNR_EL1. See B2.47 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1.

Accessing the ERXPFGCDNR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRn CRm opc2
p15, 0, <Rt>, c15, c2, 2 1111 000 1111 0010 010
Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 0, <Rt>, c15, c2, 2 x x 0 - RW n/a RW
p15, 0, <Rt>, c15, c2, 2 x 0 1 - RW RW RW
p15, 0, <Rt>, c15, c2, 2 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are applicable when accessing this register.

ERXPFGCDNR is accessible at EL3 and can be accessible at EL1 and EL2 depending on the value of bit[5] in ACTLR(S) and HACTLR. See B1.5 ACTLR, Auxiliary Control Register and B1.48 HACTLR, Hyp Auxiliary Control Register.

If EL2 or EL3 are in AArch64, then access to lower exception levels is controlled by ACTLR_EL2 or ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 and B2.7 ACTLR_EL3, Auxiliary Control Register, EL3.

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