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Register ERXPFGCDNR_EL1 accesses the ERR<n>PFGCNDR register for the error record selected by ERRSELR_EL1.SEL.
If ERRSELR_EL1.SEL==0, then ERXPFGCDNR_EL1 accesses the ERR0PFGCDNR register of the core error record. See B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register.
If ERRSELR_EL1.SEL==1, then ERXPFGCDNR_EL1 accesses the ERR1PFGCDNR register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.
ERXPFGCDNR_EL1 is architecturally mapped to AArch32 register ERXPFGCDNR. See B1.42 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register.
This register can be read using MRS with the following syntax:
This register can be written using MSR with the following syntax:
This syntax is encoded with the following settings in the instruction encoding:
This register is accessible in software as follows:
For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are applicable when accessing this register.
ERXPFGCDNR_EL1 is accessible at EL3 and can be accessible at EL1 and EL2 depending on the value of bit in ACTLR_EL2 and ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 and B2.7 ACTLR_EL3, Auxiliary Control Register, EL3.
ERXPFGCDNR_EL1 is UNDEFINED at EL0.
If ERXPFGCDNR_EL1 is accessible at EL1 and HCR_EL2.TERR == 1, then direct reads and writes of ERXPFGCDNR_EL1 at Non-secure EL1 generate a Trap exception to EL2.
If ERXPFGCDNR_EL1 is accessible at EL1 or EL2 and SCR_EL3.TERR == 1, then direct reads and writes of ERXPFGCDNR_EL1 at EL1 or EL2 generate a Trap exception to EL3.