B2.29 CPUCFR_EL1, CPU Configuration Register, EL1

The CPUCFR_EL1 provides configuration information for the core.

Bit field descriptions

CPUCFR_EL1 is a 32-bit register, and is part of the IMPLEMENTATION DEFINED registers functional group.

This register is Read Only.

Figure B2-24 CPUCFR_EL1 bit assignments
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RES0, [31:3]
Reserved, RES0.
SCU, [2]

Indicates whether the SCU is present or not. The value is:

0The SCU is present.
ECC, [1:0]

Indicates whether ECC is present or not. The possible values are:

00ECC is not present.
01ECC is present.

CPUCFR_EL1 is architecturally mapped to AArch32 register CPUCFR. See B1.19 CPUCFR, CPU Configuration Register.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Usage constraints

Accessing the CPUCFR_EL1

This register can be read with the MRS instruction using the following syntax:

MRS <Xt>,<systemreg>

To access the CPUCFR_EL1:

MRS <Xt>, CPUCFR_EL1 ; Read CPUCFR_EL1 into Xt

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C0_0 11 000 1111 0000 000

This register is accessible in software as follows:

<systemreg> Control Accessibility
S3_0_C15_C0_0 x x 0 - RO n/a RO
S3_0_C15_C0_0 x 0 1 - RO RO RO
S3_0_C15_C0_0 x 1 1 - n/a RO RO

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

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