B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2

AFSR0_EL2 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL2.

Bit field descriptions

AFSR0_EL2 is a 32-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Exception and fault handling registers functional group.
  • The IMPLEMENTATION DEFINED functional group.
Figure B2-5 AFSR0_EL2 bit assignments
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RES0, [31:0]
Reserved, RES0.
Configurations

AArch64 System register AFSR0_EL2 is architecturally mapped to AArch32 System register HADFSR. See B1.50 HADFSR, Hyp Auxiliary Data Fault Status Syndrome Register.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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