B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3

AFSR0_EL3 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL3. In the Cortex®-A55 core, no additional information is provided for these exceptions. Therefore this register is not used.

Bit field descriptions

AFSR0_EL3 is a 32-bit register, and is part of:

  • The Exception and fault handling registers functional group.
  • The Security registers functional group.
  • The IMPLEMENTATION DEFINED functional group.
Figure B2-6 AFSR0_EL3 bit assignments
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RES0, [31:0]
Reserved, RES0.

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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