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The Cortex®-A55 core simplifies the coherency logic by downgrading some memory types.
The additional attribute hints are used as follows:
Allocating reads to the L1 data cache that have the transient bit set are allocated in the L1 cache and marked as most likely to be evicted according to the L1 eviction policy.
Writes that have the transient bit set are not allocated to the L1 cache but are allocated to the L2 cache instead.
Evictions from L1 cache marked as transient are not allocated in L2 cache.
The standard CHI attributes are passed to DSU with no modifications (except for translating architectural attributes to CHI attributes):