B1.5 ACTLR, Auxiliary Control Register

The ACTLR provides access control for implementation defined registers at lower exception levels.

ACTLR is a 32-bit register, and is part of:

  • The Other system control registers functional group.
  • The Implementation defined functional group.

Bit field descriptions

The core implements the ACTLR(NS) register, but has no defined bits. This register is always RES0.

The following bit field descriptions are for the Secure version of the ACTLR.

Figure B1-1 ACTLR (S) bit assignments
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RES0, [31:13]
RES0Reserved.
CLUSTERPMUEN, [12]

Performance Management Registers enable. The value is:

0CLUSTERPM* registers are not write accessible from a lower Exception level. This is the reset value.
1CLUSTERPM* registers are write accessible from EL2.
SMEN, [11]

Scheme Management Registers enable. The value is:

0Registers CLUSTERTHREADSID, CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, and CLUSTERBUSQOS are not write accessible from EL2. This is the reset value.
1Registers controlled by the TSIDEN bit, CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, and CLUSTERBUSQOS are write accessible from EL2.
TSIDEN, [10]

Thread Scheme ID Register enable. The possible values are:

0Register CLUSTERTHREADSID is not accessible from EL1 nonsecure. This is the reset value.
1Register CLUSTERTHREADSID is accessible from EL1 nonsecure if they are write accessible from EL2.
RES0, [9:8]
RES0Reserved.
PWREN, [7]

Power Control Registers enable. The value is:

0Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write accessible from a lower Exception level. This is the reset value.
1Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write accessible from EL2.
RES0, [6]
RES0Reserved.
ERXPFGEN, [5]

Error Record Registers enable. The value is:

0ERXPFG* are not write accessible from a lower Exception level. This is the reset value.
1ERXPFG* are write accessible from EL2.
RES0, [4:2]
RES0Reserved.
ECTLREN, [1]

Extended Control Registers enable. The value is:

0CPUECTLR and CLUSTERECTLR are not write accessible from a lower Exception level. This is the reset value.
1CPUECTLR and CLUSTERECTLR are write accessible from EL2.
ACTLREN, [0]

Auxiliary Control Registers enable. The value is:

0CPUACTLR and CLUSTERACTLR are not write accessible from a lower Exception level. This is the reset value.
1CPUACTLR and CLUSTERACTLR are write accessible from EL2.
Configurations

AArch32 register ACTLR(NS) is mapped to AArch64 register ACTLR_EL1. See B2.5 ACTLR_EL1, Auxiliary Control Register, EL1.

AArch32 register ACTLR(S) is mapped to AArch64 register ACTLR_EL3. See B2.7 ACTLR_EL3, Auxiliary Control Register, EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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