B1.7 ADFSR, Auxiliary Data Fault Status Register

The ADFSR provides extra implementation defined fault status information for Data Abort exceptions taken to EL1 modes. In the Cortex®-A55 core, no additional information is provided for such exceptions, so this register is not used.

Bit field descriptions

ADFSR is a 32-bit register, and is part of:

  • The Exception and fault handling registers functional group.
  • The Implementation defined functional group.
Figure B1-3 ADFSR bit assignments
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[31:0]
Reserved, RES0.
Configurations

AArch32 System register ADFSR is architecturally mapped to AArch64 System register AFSR0_EL1. See B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1.

AArch32 register ADFSR(S) is architecturally mapped to AArch64 register AFSR0_EL3. See B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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