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When using the Long-descriptor format translation tables for stage 1 translations, AMAIR0 provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR0. This register is not used in the Cortex®-A55 core.
AMAIR0 is a 32-bit register, and is part of:
AArch32 System register AMAIR0 is architecturally mapped to AArch64 System register AMAIR_EL1[31:0]. See B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1.
AArch32 System register AMAIR0(S) is architecturally mapped to AArch64 System register AMAIR_EL3[31:0]. See B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.