B1.12 AMAIR1, Auxiliary Memory Attribute Indirection Register 1

When using the Long-descriptor format translation tables for stage 1 translations, AMAIR1 provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR1. This register is not used in the Cortex®-A55 core.

Bit field descriptions

AMAIR1 is a 32-bit register, and is part of:

  • The Virtual memory control registers functional group.
  • The Implementation defined functional group.
Figure B1-8 AMAIR1 bit assignments
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RES0, [31:0]
RES0Reserved.
Configurations

AArch32 System register AMAIR1 is architecturally mapped to AArch64 System register AMAIR_EL1[63:32]. See B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1.

AArch32 System register AMAIR1(S) is architecturally mapped to AArch64 System register AMAIR_EL3[63:32]. See B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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